SLUS920A July 2009 – July 2015
The bq24753A device is a host-controlled, Li-ion or Li-polymer battery charger with integrated compensation and system power selector logic. The device employs a switched-mode synchronous buck PWM controller with constant switching frequency. The device controls external switches to prevent battery discharge back to the input, connect the adapter to the system, and connect the battery to the system using 6-V gate drives for better system efficiency. The bq24753A features Dynamic Power Management (DPM) which reduces battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying current to the system and the battery charger simultaneously. A highly accurate current-sense amplifier enables precise measurement of input current from the AC adapter to monitor the overall system power. The input current limit can be configured through the ACSET pin of the device. Ratiometric charge current and voltage programming allows for high regulation accuracies, and can be either hardwired with resistors or programmed by the system power-management microcontroller using a DAC or GPIOs.
The bq24753A uses a high-accuracy voltage regulator for charging voltage. Internal default battery voltage setting VBATT = 4.2 V × cell count. The regulation voltage is ratiometric with respect to VADC. The ratio of VADJ and VDAC provides extra 12.5% adjust range on VBATT regulation voltage. By limiting the adjust range to 12.5% of the regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, while using 1% mismatched resistors. Ratiometric conversion also allows compatibility with D/As or microcontrollers (μC). The battery voltage is programmed through VADJ and VDAC using Equation 1:
The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. VBATT defaults to 4.2 V × cell count when VADJ is connected to REGN.
The CELLS pin is the logic input for selecting the cell count. Connect CELLS to the appropriate voltage level to charge 2,3, or 4 Li+ cells, as shown in Table 2. When charging other cell chemistries, use CELLS to select an output voltage range for the charger.
The per-cell charge-termination voltage is a function of the battery chemistry. Consult the battery manufacturer to determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, or directly on the output capacitor. A 0.1-μF ceramic capacitor from BAT to AGND is recommended to be as close to the BAT pin as possible to decouple high-frequency noise.
The SRSET input sets the maximum charge current. Battery current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010-Ω sense resistor, the maximum charging current is 10 A. SRSET is ratiometric with respect to VDAC using Equation 2:
The input voltage range of SRSET is between 0 and VDAC, up to 3.6 V.
The SRP and SRN pins are used to sense across RSR, with a default value of 10 mΩ. However, resistors of other values can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy. However, this is at the expense of a higher conduction loss.
The total input current from an AC adapter or other DC sources is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the systems are powered up or down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging current when the input current exceeds the input current limit set by ACSET. The current capacity of the AC adapter can be lowered, reducing system cost.
Similar to setting battery-regulation current, adapter current is sensed by resistor RAC connected between ACP and ACN. Its maximum value is set by ACSET, which is ratiometric with respect to VDAC, using Equation 3:
The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V.
The ACP and ACN pins are used to sense RAC with a default value of 10 mΩ. However, resistors of other values can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy. However, this is at the expense of a higher conduction loss.
An external resistor voltage divider attenuates the adapter voltage to the ACDET pin. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage and lower than the minimum-allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense the true adapter input voltage whether the ACFET is on or off. Before the adapter is detected, BATFET stays on and ACFET turns off.
If PVCC is below 4 V, the device is disabled. If ACDET is below 0.6 V but PVCC is above 4 V, part of the bias is enabled, including a crude bandgap reference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescent current is less than 10 μA.
When ACDET rises above 0.6 V and PVCC is above 4 V, all the bias circuits are enabled and VREF rises to 3.3 V, and the REGN output rises to 6 V when CHGEN is LOW. IADAPT becomes valid to proportionally reflect the adapter current.
When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 700 ms later, the following occurs:
The following conditions must be valid before the charge function is enabled:
The bq24753A automatically switches between connecting the adapter or battery power to the system load. By default, the battery is connected to the system during power up or when a valid adapter is not present. When the adapter is detected, the battery is first disconnected from the system, then the adapter is connected. An automatic break-before-make algorithm prevents shoot-through currents when the selector transistors switch.
The ACDRV signal drives a pair of back-to-back p-channel power MOSFETs (with sources connected together and to PVCC) connected between the adapter and ACP. The FET connected to the adapter prevents reverse discharge from the battery to the adapter when it is turned off. The p-channel FET with the drain connected to the adapter input provides reverse battery discharge protection when off; and also minimizes system power dissipation, with its low RDS(on), compared to a Schottky diode. The other p-channel FET connected to ACP separates the battery from the adapter, and provides both ACOC current limit and ACOP power limit to the system. The BATDRV signal controls a p-channel power MOSFET placed between BAT and the system.
When the adapter is not detected, the ACDRV output is pulled to PVCC to turn off the ACFET, disconnecting the adapter from system. BATDRV stays at ACN – 6 V to connect the battery to the system.
At 700 ms after adapter is detected, the system begins to switch from the battery to the adapter. The PVCC voltage must be 185 mV above BAT to enable the switching. The break-before-make logic turns off both ACFET and BATFET for 10μs before ACFET turns on. This isolates the battery from shoot-through current or any large discharging current. The BATDRV output is pulled up to ACN and the ACDRV pin is set to PVCC – 6 V by an internal regulator to turn on the p-channel ACFET, connecting the adapter to the system.
When the adapter is removed, the system waits till ACN drops back to within 285 mV above BAT to switch from the adapter back to the battery. The break-before-make logic ensures a 10-μs dead time. The ACDRV output is pulled up to PVCC and the BATDRV pin is set to ACN – 6 V by an internal regulator to turn on the p-channel BATFET, connecting the battery to the system.
Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turn-off and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power MOSFETs.
To keep BATDRV on when adaptor is removed, do not apply extermal voltage source on VREF pin.
A battery Learn cycle can be implemented using the LEARN pin. A logic low on LEARN keeps the system power selector logic in its default states dependant on the adapter. If adapter is not detected, then; the ACFET is kept off, and the BATFET is kept on. If the adapter is detected, the BATFET is kept off, and the ACFET is kept on.
When the LEARN pin is at logic high, the system power selector logic is overridden, keeping the ACFET off and the BATFET on when the adapter is present. This is used to allow the battery to discharge in order to calibrate the battery gas gauge over a complete discharge/charge cycle. Charge turns off when LEARN is high. The controller automatically exits the learn cycle when BAT < 2.9 V per cell. BATDRV turns off and ACDRV turns on.
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-up the charge regulation current into 8 evenly-divided steps up to the programmed charge current. Each step lasts approximately 1 ms, for a typical rise time of 8 ms. No external components are needed for this function.
The synchronous-buck PWM converter uses a fixed-frequency (300 kHz) voltage mode with a feed-forward control scheme. A Type-III compensation network allows the use of ceramic capacitors at the output of the converter. The compensation input stage is internally connected between the feedback output (FBO) and the error-amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected for a nominal resonant frequency of 8 kHz–12.5 kHz.
The resonant frequency, fo, is given by:
where (from Figure 37):
CO = C11 + C12
LO = L1
An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the converter. The ramp height is one-fifteenth of the input adapter voltage, making it always directly proportional to the input adapter voltage. This cancels out any loop-gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset by 200 mV in order to allow a 0% duty cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to operate with a 100% duty-cycle PWM request. Internal gate-drive logic allows a 99.98% duty-cycle while ensuring that the N-channel upper device always has enough voltage to stay fully on. If the BTST-to-PH voltage falls below 4 V for more than 3 cycles, the high-side N-channel power MOSFET is turned off and the low-side N-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected falling low again due to leakage current discharging the BTST capacitor below 4 V, and the reset pulse is reissued.
The 300-kHz fixed-frequency oscillator tightly controls the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature. This simplifies output-filter design, and keeps it out of the audible noise region. The charge-current sense resistor RSR should be designed with at least half or more of the total output capacitance placed before the sense resistor, contacting both sense resistor and the output inductor; and the other half, or remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed on both sides of the charge-current sense resistor. A ratio of 50:50 percent gives the best performance; but the node in which the output inductor and sense resistor connect should have a minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better current-sense accuracy. The Type-III compensation provides phase boost near the cross-over frequency, giving sufficient phase margin.
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET internal setting value. Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side N-channel power MOSFET is on when the high-side N-channel power MOSFET is off. The internal gate-drive logic uses break-before-make switching to prevent shoot-through currents. During the 30-ns dead time where both FETs are off, the back-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safe charging at high currents. During synchronous mode, the inductor current always flows, and the device operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the break-before-make dead-time, the low-side n-channel power MOSFET turns on for approximately 80 ns, then the low-side power MOSFET turns off and stays off until the beginning of the next cycle, when the high-side power MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure that the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from flowing. The inductor current is blocked by the turned-off low-side MOSFET, and the inductor current becomes discontinuous. This mode is called Discontinuous Conduction Mode (DCM).
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means that at low currents, the loop response is slower, because there is less sinking current available to discharge the output voltage. At low currents during non-synchronous operation, there may be a small amount of negative inductor current during the 80-ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance. When BTST – PH < 4 V, the 80-ns recharge pulse occurs on LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (only 80-ns recharge pulse).
In the bq24753A, VISYNSET = ISYN × RSR is internally set to 13 mV as the charge-current threshold at which the charger changes from non-synchronous operation to synchronous operation. The low-side driver turns on for only 80 ns to charge the boost capacitor. This is important to prevent negative inductor current, which may cause a boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors. This boost effect can lead to an overvoltage on the PVCC node and potentially damage the system. The inductor ripple current is given by:
|VIN =||adapter voltage|
|VBAT =||BAT voltage|
|fS =||switching frequency|
|L =||output inductor|
|D =||VBAT/VIN, duty-cycle|
IRIPPLE_MAX happens when the duty cycle (D) value is close to 0.5 at given VIN, fS, and L.
The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between SRP-SRN and the internal threshold. The threshold is set to 13 mV on the falling edge with an 8-mV hysteresis on the rising edge with a 10% variation.
An industry-standard, high-accuracy current sense amplifier (CSA) is used by the host or some discrete logic to monitor the input current through the analog voltage output of the IADAPT pin. The CSA amplifies the sensed input voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times the input differential voltage. When PVCC is above 5 V and ACDET is above 0.6 V, IADAPT no longer stays at ground, but becomes active. If the user wants to lower the voltage, they can use a resistor divider from IOUT to AGND, and still achieve accuracy over temperature as the resistors can be matched according to their thermal coefficients.
A 100-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional RC filter is optional, after the 100-pF capacitor, if additional filtering is desired. Note that adding filtering also adds additional response delay.
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage is above the programmable OVPSET voltage (3.1 V), charge is disabled, the adapter is disconnected from the system by turning off ACDRV, and the battery is connected to the system by turning on BATDRV. ACOV is not latched—normal operation resumes when the OVPSET voltage returns below 3.1 V.
The system must have 4 V minimum of PVCC voltage for proper operation. This PVCC voltage can come from either the input adapter or the battery, using a diode-OR input. When the PVCC voltage is below 4 V, the bias circuits REGN, VREF, and the gate drive bias to ACFET and BATFET stay inactive, even with ACDET above 0.6 V.
ACLOWV clears the break-before-make protection latch when ACP < 3 V in addition to UVLO clearing this latch when PVCC < UVLO. It ensures the BATDRV is off when ACP < 3 V, and thus this function allows the ACDRV to turn on the ACFET again when ACP < 3 V or PVCC <UVLO.
The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is disconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging the stored output-inductor energy into the output capacitors.
The bq24753A has a BAT_SHORT comparator monitoring the output battery voltage (BAT). If the voltage falls below 2.9 V per cell (5.8 V for 2 cells, 8.7 V for 3 cells, 11.6 V for 4 cells), a battery-short status is detected. Below the BAT_SHORT threshold, the charger reduces the charge current to 1/8th of the programmed charging current (0.1×SRSET/VDAC)/8 = C/8 down to zero volts on BAT pin.. This lower current is used as a pre-charge current for over-discharged battery packs. Above the BAT_SHORT threshold (plus hysteresis, the charge current resumes at the programmed value (0.1×SRSET/VDAC).
The BAT_SHORT comparator also serves as a depleted-battery alarm during a LEARN cycle. If the selector is in a LEARN cycle, and the battery voltage falls bellow the BAT_SHORT threshold, the selector disconnects the battery from the system and connects the adapter to the system in order to protect the battery pack. If battery voltage increases, and LEARN is still logic high, then the selector disconnects the adapter from the system and reconnects the battery to the system.
The charger has a secondary overcurrent protection feature. It monitors the charge current, and prevents the current from exceeding 145% of regulated charge current. The high-side gate drive turns off when the overcurrent is detected, and automatically resumes when the current falls below the overcurrent threshold.
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off and self-protects when the junction temperature exceeds the TSHUT threshold of 155°C. The charger stays off until the junction temperature falls below 135°C.
One status output is available, and it requires an external pullup resistor to pull the pin to the system digital rail for a high level.
ACGOOD goes low after the deglitch time delay when ACDET is above 2.4 V and PVCC is above BAT + 185 mV. It indicates that the adapter voltage is high enough for normal operation.
The ACOC/ACOP circuit provides a reliable layer of safety protection that can complement other safety measures. ACOC/ACOP helps to protect from input current surge due to various conditions including:
Several examples of the circuit protecting from these fault conditions are shown below.
For designs using the selector functions, an input overcurrent (ACOC) and input overpower protection function (ACOP) is provided. The threshold is set by an external capacitor from the ACOP pin to AGND. After the adapter is detected (ACDET pin > 2.4 V), there is a 700-ms delay before ACGOOD is asserted low, and Q3 (BATFET) is turned-off. Then Q1/Q2 (ACFET) are turned on by the ACDRV pin. When Q1/Q2 (ACFET) are turned on, the ACFET allows operation in linear-regulation mode to limit the maximum input current, ACOC, to a safe level. The ACOC current limit is 2.65 times the programmed DPM input current limit set by the ratio of ACSET/VDAC. The maximum allowable current limit is 100 mV across ACP – ACN (10 A for a 10-mΩ sense resistor).
The first 2 ms after the ACDRV signal begins to turn on, ACOC may limit the current; but the controller is not allowed to latch off in order to allow a reasonable time for the system voltage to rise.
After 2 ms, ACOP is enabled. ACOP allows the ACFET to latch off before the ACFET can be damaged by excessive thermal dissipation. The controller only latches if the ACOP pin voltage exceeds 2 V with respect to AGND. In ACOP, a current source begins to charge the ACOP capacitor when the input current is being limited by ACOC. This current source is proportional to the voltage across the source-drain of the ACFET (VPVCC-ACP) by an 18-μA/V ratio. This dependency allows faster capacitor charging if the voltage is larger (more power dissipation). It allows the time to be programmed by the ACOP capacitor selected. If the controller is not limiting current, a fixed 5-μA sink current into the ACOP pin to discharge the ACOP capacitor. This charge and discharge effect depends on whether there is a current-limit condition, and has a memory effect that averages the power over time, protecting the system from potentially hazardous repetitive faults. Whenever the ACOP threshold is exceeded, the charge is disabled and the adapter is disconnected from the system to protect the ACFET and the whole system. If the ACFET is latched off, the BATFET is turned on to connect the battery to the system.
The capacitor provides a predictable time to limit the power dissipation of the ACFET. Since the input current is constant at the ACOC current limit, the designer can calculate the power dissipation on the ACFET.
The ACOC current Limit threshold is equal to:
The time it takes to charge to 2 V can be calculated from:
An ACOP fault latch off can only be cleared by bringing the ACDET pin voltage below 2.4 V, then above 2.4 V (for example, remove adapter and reinsert), or by reducing the PVCC voltage below the UVLO threshold and raising it.
702 ms after ACDET (adapter detected), and: