ADS62P28 デュアル・チャネル、12 ビット、210MSPS ADC、DDR LVDS/パラレル CMOS 出力 | TIJ.co.jp

ADS62P28
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デュアル・チャネル、12 ビット、210MSPS ADC、DDR LVDS/パラレル CMOS 出力

 

概要

The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

特長

  • Maximum Sample Rate: 250 MSPS
  • 14-Bit Resolution – ADS62P49/ADS62P48
  • 12-Bit Resolution – ADS62P29/ADS62P28
  • Total Power: 1.25 W at 250 MSPS
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Gain up to 6dB for SNR/SFDR Trade-Off
  • DC Offset Correction
  • 90dB Cross-Talk
  • Supports Input Clock Amplitude Down to 400 mVPP Differential
  • Internal and External Reference Support
  • 64-QFN Package (9 mm × 9 mm)

機能一覧

他の製品と比較 高速 ADCs (>10MSPS) メール Excelへダウンロード
Part number オーダー・オプション Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS62P28 ご注文 210     High Performance     12     2     70.8     11.1     98     1140     2     DDR LVDS
Parallel CMOS    
-40 to 85     700     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P15 サンプルは利用できません。 125     Low Power     11     2     67.2     10.8     89     740     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P19 サンプルは利用できません。 250     High Performance     11     2     66.5     10.6     98     1250     2     DDR LVDS
Parallel CMOS    
-40 to 85     700     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P22 サンプルは利用できません。 65     High Performance     12     2     71.6     11.5     94     518     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P23 サンプルは利用できません。 80     High Performance     12     2     71.6     11.6     93     587     2