SN74AVCH1T45 1 ビット、デュアル電源 バス・トランシーバ、可変 レベル・トランスレーション/3 ステート出力 | TIJ.co.jp

SN74AVCH1T45
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1 ビット、デュアル電源 バス・トランシーバ、可変 レベル・トランスレーション/3 ステート出力

 

概要

The SN74AVCH1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH1T45 is designed for asynchronous communication between two data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input.

The SN74AVCH1T45 is designed so that the DIR input is referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

特長

  • Available in the Texas Instruments NanoStar&trade
    and NanoFree™ Packages
  • Control Inputs (DIR) VIH and VIL Levels Are
    Referenced to VCCA Voltage
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup and Pulldown Resistors
  • VCC Isolation
  • Fully Configurable Dual-Rail Design
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Typical Max Data Rates
    • 500 Mbps (1.8-V to 3.3-V Translation)
    • 320 Mbps (<1.8-V to 3.3-V Translation)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • Human-Body Model (A114-A): 2000 V
    • Machine Model (A115-A): 200 V
    • Charged-Device Model (C101): 1000 V

機能一覧

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Part number オーダー・オプション Technology Family Application Bits (#) High input voltage (Min) (Vih) High input voltage (Max) (Vih) Output voltage (Min) (V) Output voltage (Max) (V) IOH (Max) (mA) IOL (Max) (mA) Package Group Rating
SN74AVCH1T45 ご注文 AVC     GPIO     1     1     3.6     1.2     3.6     -12     12     DSBGA | 6
SC70 | 6
SOT-23 | 6    
Catalog    
SN74AVC1T45 ご注文 AVC     GPIO     1     0.78     3.6     1.2     3.6     -12     12     DSBGA | 6
SC70 | 6
SOT-23 | 6
SOT-5X3 | 6    
Catalog    
SN74AVCH16T245 ご注文 AVC       16     1     3.6     1.2     3.6     -12     12     TSSOP | 48
TVSOP | 48    
Catalog    
SN74AVCH20T245 ご注文 AVC       20     0.8     3.6     1.2     3.6     -12     12     TSSOP | 56
TVSOP | 56    
Catalog    
SN74AVCH2T45 ご注文 AVC     GPIO
I2S    
2     0.8     3.6     1.2     3.6     -12     12     DSBGA | 8
SM8 | 8
VSSOP | 8    
Catalog    
SN74AVCH4T245 ご注文 AVC     UART
JTAG
SPI    
4     1.2     3.6     1.2     3.6     -12     12     SOIC | 16
TSSOP | 16
TVSOP | 16
UQFN | 16
VQFN | 16    
Catalog    
SN74AVCH8T245 ご注文 AVC