The SN74LVC1G132 device contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V VCC operation and performs the Boolean function Y = A × B or Y = A + B in positive logic.
Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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|Part number||オーダー・オプション||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Inputs per channel||IOL (Max) (mA)||IOH (Max) (mA)||Input type||Output type||Features||Rating||Data rate (Max) (Mbps)||Operating temperature range (C)||Package size: mm2:W x L (PKG)||Package Group|
Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)
|Catalog||100||-40 to 125||
5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)
5SOT-23: 5 mm2: 1.6 x 2.9 (SOT-23 | 5)
SC70 | 5
SOT-23 | 5