JAJSHZ0A April   2013  – September 2019 TMP108

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
      1. 6.6.1 Two-Wire Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interface
      2. 7.3.2 Serial Bus Address
      3. 7.3.3 Bus Overview
      4. 7.3.4 Writing and Reading Operation
      5. 7.3.5 Slave Mode Operations
        1. 7.3.5.1 Slave Receiver Mode:
        2. 7.3.5.2 Slave Transmitter Mode:
      6. 7.3.6 SMBus Alert Function
      7. 7.3.7 General Call
      8. 7.3.8 High-Speed (Hs) Mode
      9. 7.3.9 Timeout Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (M1 = 0, M0 = 0)
      2. 7.4.2 One-Shot Mode (M1 = 0, M0 = 1)
      3. 7.4.3 Continuous Conversion Mode (M1 = 1)
    5. 7.5 Programming
      1. 7.5.1 Pointer Register
      2. 7.5.2 Temperature Register
      3. 7.5.3 Configuration Register
        1. 7.5.3.1 Hysteresis Control (HYS1 and HYS0)
        2. 7.5.3.2 Polarity (POL)
        3. 7.5.3.3 Thermostat Mode (TM)
        4. 7.5.3.4 Temperature Watchdog Flags (FL and FH)
        5. 7.5.3.5 Conversion Rate
      4. 7.5.4 High- and Low-Limit Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Diagrams

The TMP108 is two-wire and SMBus compatible. Figure 1 to Figure 4 describe the various operations on the TMP108. Parameters for Figure 1 are defined in Table 1. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high defines a start condition. Each data transfer is initiated with a start condition.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a stop condition. Each data transfer is terminated with a repeated start or stop condition.

Data Transfer: The number of data bytes transferred between a start and a stop condition is not limited, and is determined by the master device. The receiver acknowledges the transfer of data. It is also possible to use the TMP108 for single-byte updates. To update only the MS byte, terminate communication by issuing a start or stop condition on the bus.

Acknowledge: Each receiving device, when addressed, must generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a master receives data, the termination of the data transfer can be signaled by the master generating a not-acknowledge (1) on the last byte transmitted by the slave.

Table 1. Timing Diagram Definitions

FAST MODE HIGH-SPEED MODE UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency, V+ ≥ 1.8 V 0.001 0.4 0.001 3.4 MHz
SCL operating frequency, V+ < 1.8 V 0.001 0.4 0.001 2.5 MHz
t(BUF) Bus free time between stop and start conditions, V+ ≥ 1.8 V 1300 160 ns
Bus free time between stop and start conditions, V+ < 1.8 V 1300 260 ns
t(HDSTA) Hold time after repeated start condition.
After this period, the first clock is generated.		 600 160 ns
t(SUSTA) Repeated start condition setup time 600 160 ns
t(SUSTO) Stop condition setup time 600 160 ns
t(HDDAT) Data hold time, V+ ≥ 1.8 V 0 900 0 70 ns
Data hold time, V+ < 1.8 V 0 900 0 130 ns
t(SUDAT) Data setup time, V+ ≥ 1.8 V 100 10 ns
Data setup time, V+ < 1.8 V 100 50 ns
t(LOW) SCL clock low period, V+ ≥ 1.8 V 1300 160 ns
SCL clock low period, V+ < 1.8 V 1300 260 ns
t(HIGH) SCL clock high period 600 60 ns
tR , tF - SDA Data rise/fall time 300 80 ns
tR , tF - SCL Clock rise/fall time 300 40 ns
tR Clock/data rise time for SCLK ≤ 100 kHz 1000 ns