ADC32RF42
Dual-Channel, 14-Bit, 1.5-GSPS RF-Sampling Analog-to-Digital Converter (ADC)
ADC32RF42
- 14-Bit, Dual-Channel, 1.5-GSPS ADC
- Noise Floor: –151.8 dBFS/Hz
- RF Input Supports Up to 4 GHz
- Aperture Jitter: 90 fS
- Channel Isolation: 95 dB at fIN = 1.8 GHz
- Spectral Performance (fIN = 950 MHz, –2 dBFS):
- SNR: 61.1 dBFS
- SFDR: 67-dBc HD2, HD3
- Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
- SNR: 58.9 dBFS
- SFDR: 64-dBc HD2, HD3
- On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
- On-Chip Input Clamp for Overvoltage Protection
- Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
- On-Chip Dither
- On-Chip Input Termination
- Input Full-Scale: 1.35 VPP
- Support for Multi-Chip Synchronization
- JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel Up to 12.5 Gbps
- Power Dissipation: 2 W/Ch at 1.5 GSPS
- 72-Pin VQFN Package (10 mm × 10 mm)
The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | ADC32RF42 Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter datasheet | PDF | HTML | 16 May 2017 |
EVM User's guide | ADC32RFxxEVM User's Guide (Rev. E) | 31 Jan 2020 | ||
Application note | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | 05 Sep 2017 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
ADC32RF42EVM — ADC32RF42 Dual-Channel, 14-Bit, 1.5GSPS, RF-Sampling ADC Evaluation Module
The ADC32RF42 evaluation module (EVM) demonstrates the performance of a dual 1.5-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF42 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)
TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
Supported products & hardware
Products
Receivers
High-speed ADCs (≥10 MSPS)
RF-sampling transceivers
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
VQFNP (RMP) | 72 | View options |
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