TXV0108
- Configurable design allows each port to operate with a power supply range from 1.14V to 3.6V
- Supports up to 500Mbps for 1.65V to 3.6V
- Meets RGMII 2.0 timing specifications:
- < 750ps rise and fall time
- < ± 5 % duty cycle distortion
- < ± 400 ps channel to channel skew
- Up to 250Mbps/Channel
-
Integrated 10 Ω damping output resistor to minimize signal reflections
-
High drive strength (up to 12mA at 3.6V)
- Fully configurable symmetric dual-rail design
- Optimal signal integrity performance with 390ps peak-to-peak jitter for 1.8V to 3.3V
- Features VCC isolation and VCC disconnect
- Ioff supports partial-power-down mode operation
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD protection exceeds JESD 22:
- 2000V Human-Body Model
- 1000V Charged-Device Model
- Low power consumption:
- 10µA maximum (25°C)
- 20µA maximum (–40°C to 125°C)
- Operating temperature from –40°C to +125°C
- Pin compatible with SN74AVC8T245 (VQFN)
The TXV0108 is an 8-bit, dual-supply direction controlled low-skew, low-jitter voltage translation device. This device can be used for redriving, voltage translation, and power isolation when implementing skew sensitive interface, such as RGMII between Ethernet MAC and PHY devices. The Ax I/O pins and control pins (DIR, OE) are referenced to VCCA logic levels, and Bx I/O pins are referenced to VCCB logic levels. This device has improved channel-to-channel skew, duty cycle distortion and symmetric rise and fall time for applications requiring strict timing conditions.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature is designed so that if either VCC supply is at or near 0V both ports will switch to a high-impedance state. This feature enables power isolation for communications across multiple MACs and PHYs, and is beneficial in situations where MACs and PHYs are powered up asynchronously preventing current backflow between devices.
A High on DIR allows data transmission from A to B while a Low on DIR allows data transmission from B to A when OE is set to Low. When OE is set to High, both Ax and Bx pins will be forced into a high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.
技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | データシート | TXV0108 8-Bit Direction Controlled Low-Skew, Low-Jitter Voltage Translator or Buffer データシート (Rev. A) | PDF | HTML | 2024年 4月 12日 | ||
EVM ユーザー ガイド (英語) | TXV010xEVM Evaluation Module User's Guide | PDF | HTML | 2024年 2月 5日 | |||
アプリケーション・ノート | Overcoming Design Challenges - Implementing High Performance Interfaces | PDF | HTML | 2023年 12月 12日 | |||
アプリケーション概要 | Supporting Time and Skew Sensitive Interfaces with TI's TXV Level-Shifter | PDF | HTML | 2023年 10月 27日 | |||
アプリケーション概要 | Enabling Industrial and Automotive Ethernet RGMII Interfaces with Voltage Transl | PDF | HTML | 2023年 8月 2日 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
14-24-NL-LOGIC-EVM — 14 ピンから 24 ピンのリードなしパッケージ向け、ロジック製品の汎用評価基板
14-24-NL-LOGIC-EVM は、14 ピンから24 ピンの BQA、BQB、RGY、RSV、RJW、RHL の各パッケージに封止した各種ロジック デバイスや変換デバイスをサポートする設計を採用したフレキシブルな評価基板 (EVM) です。
TXV0108-EVM — TXV0108 の評価基板
パッケージ | ピン数 | ダウンロード |
---|---|---|
VQFN (RGY) | 24 | オプションの表示 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 材質成分
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点