TMS320C6654 (供給中)

固定および浮動小数点、デジタル・シグナル・プロセッサ

固定および浮動小数点、デジタル・シグナル・プロセッサ - TMS320C6654
 

概要

The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI's KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 27.2 GMACS per core and 13.6 GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI's previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces, PCI Express Gen2, and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO.

The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

特長

  • One TMS320C66x DSP Core Subsystem (CorePac)
    • C66x Fixed- and Floating-Point CPU Core: Up to 850 MHz for C6654 and 600 MHz for C6652
  • Multicore Shared Memory Controller (MSMC)
    • Memory Protection Unit for DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Peripherals
    • PCIe Gen2 (C6654 Only)
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • Gigabit Ethernet (GbE) Subsystem (C6654 Only)
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1066
      • 8GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

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詳細を表示

機能一覧 他の製品と比較 C66x DSP

 
Applications
DSP
DSP MHz (Max)
DSP GFLOPS
Total On-Chip Memory (KB)
On-Chip L2 Cache/RAM
EMAC
PCI/PCIe
Serial I/O
Operating Temperature Range (C)
DRAM
Other On-Chip Memory
Hardware Accelerators
Package Size: mm2:W x L (PKG)
TMS320C6654 TMS320C6652 TMS320C6655 TMS320C6657
Grid Infrastructure
Machine Vision    
Machine Vision     Avionics & Defense
Machine Vision    
Avionics & Defense
Communications
Machine Vision    
1 C66x     1 C66x     1 C66x     2 C66x    
750
850    
600     1000
1250    
1000
1250    
12
13.6    
9.6     16
20    
32
40    
1088     1088     2278     3200    
1024 KB     1024 KB     1024 KB     2048 KB    
10/100/1000     N/A     10/100/1000     10/100/1000    
2 PCIe Gen2     N/A     2 PCIe Gen2     2 PCIe Gen2    
I2C
SPI
UART
UPP    
I2C
SPI
UART
UPP    
Hyperlink
I2C
RapidIO
SPI
TSIP
UART    
Hyperlink
I2C
RapidIO
SPI
TSIP
UART    
-40 to 100
0 to 85    
-40 to 100
0 to 85    
-40 to 100
0 to 85    
-40 to 100
0 to 85    
DDR3     DDR3     DDR3     DDR3    
1024 KB     1024 KB     1024 KB     1024 KB    
0     0     TCP3d
VCP2    
TCP3d
VCP2    
See datasheet (FCBGA)     See datasheet (FCBGA)     See datasheet (FCBGA)     See datasheet (FCBGA)