SPRSP35G February   2019  – March 2021 DRA829J , DRA829V

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW9G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EHRPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
      22. 6.3.22 UFS
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 PRU_ICSSG [Currently Not Supported]
        1. 6.3.23.1 MAIN Domain
      24. 6.3.24 MCASP
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 DSS
        1. 6.3.25.1 MAIN Domain
      26. 6.3.26 DP
        1. 6.3.26.1 MAIN Domain
      27. 6.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 6.3.27.1 MAIN Domain
      28. 6.3.28 DSI_TX
        1. 6.3.28.1 MAIN Domain
      29. 6.3.29 VPFE
        1. 6.3.29.1 MAIN Domain
      30. 6.3.30 DMTIMER
        1. 6.3.30.1 MAIN Domain
        2. 6.3.30.2 MCU Domain
      31. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
      32. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode Configuration
          1. 6.3.32.1.1 MAIN Domain
          2. 6.3.32.1.2 MCU Domain
        2. 6.3.32.2 Clock
          1. 6.3.32.2.1 MAIN Domain
          2. 6.3.32.2.2 WKUP Domain
        3. 6.3.32.3 System
          1. 6.3.32.3.1 MAIN Domain
          2. 6.3.32.3.2 WKUP Domain
        4. 6.3.32.4 EFUSE
      33. 6.3.33 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 USB2PHY Electrical Characteristics
      2. 7.7.2 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      3. 7.7.3 UFS M-PHY Electrical Characteristics
      4. 7.7.4 eDP/DP AUX-PHY Electrical Characteristics
      5. 7.7.5 DDR0 Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for ALF Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Independent MCU and Main Domains, Primary Power- Down Sequencing
        6. 7.10.2.6 Entry and Exit of MCU Only State
        7. 7.10.2.7 Entry and Exit of DDR Retention State
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
          6. 7.10.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 7.10.4.1.7 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Device Inputs and Outputs Module Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  VPFE
        3. 7.10.5.3  CPSW2G
          1. 7.10.5.3.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.3.2 CPSW2G RMII Timings
            1. 7.10.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.3.3 CPSW2G RGMII Timings
            1. 7.10.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 7.10.5.4  CPSW9G
          1. 7.10.5.4.1 CPSW9G MDIO Interface Timings
          2. 7.10.5.4.2 CPSW9G RMII Timings
            1. 7.10.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 7.10.5.4.3 CPSW9G RGMII Timings
            1. 7.10.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 7.10.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 7.10.5.5  CSI-2
        6. 7.10.5.6  DDRSS
        7. 7.10.5.7  DSS
        8. 7.10.5.8  eCAP
          1. 7.10.5.8.1 Timing Requirements for eCAP
          2. 7.10.5.8.2 Switching Characteristics for eCAP
        9. 7.10.5.9  EPWM
          1. 7.10.5.9.1 Timing Requirements for eHRPWM
          2. 7.10.5.9.2 Switching Characteristics for eHRPWM
        10. 7.10.5.10 eQEP
          1. 7.10.5.10.1 Timing Requirements for eQEP
          2. 7.10.5.10.2 Switching Characteristics for eQEP
        11. 7.10.5.11 GPIO
          1. 7.10.5.11.1 GPIO Timing Requirements
          2. 7.10.5.11.2 GPIO Switching Characteristics
        12. 7.10.5.12 GPMC
          1. 7.10.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        13. 7.10.5.13 HyperBus
          1. 7.10.5.13.1 Timing Requirements for HyperBus
          2. 7.10.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 7.10.5.14 I2C
        15. 7.10.5.15 I3C
        16. 7.10.5.16 MCAN
        17. 7.10.5.17 MCASP
        18. 7.10.5.18 MCSPI
          1. 7.10.5.18.1 MCSPI — Master Mode
          2. 7.10.5.18.2 MCSPI — Slave Mode
        19. 7.10.5.19 MMCSD
          1. 7.10.5.19.1 MMC0 - eMMC Interface
            1. 7.10.5.19.1.1 Legacy SDR Mode
            2. 7.10.5.19.1.2 High Speed SDR Mode
            3. 7.10.5.19.1.3 High Speed DDR Mode
            4. 7.10.5.19.1.4 HS200 Mode
          2. 7.10.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.19.2.1 Default Speed Mode
            2. 7.10.5.19.2.2 High Speed Mode
            3. 7.10.5.19.2.3 UHS–I SDR12 Mode
            4. 7.10.5.19.2.4 UHS–I SDR25 Mode
            5. 7.10.5.19.2.5 UHS–I SDR50 Mode
            6. 7.10.5.19.2.6 UHS–I DDR50 Mode
        20. 7.10.5.20 CPTS
          1. 7.10.5.20.1 CPTS Timing Requirements
          2. 7.10.5.20.2 CPTS Switching Characteristics
        21. 7.10.5.21 OSPI
          1. 7.10.5.21.1 OSPI With Data Training
            1. 7.10.5.21.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.21.2 OSPI Without Data Training
            1. 7.10.5.21.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.10.5.21.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.10.5.21.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.10.5.21.2.4 OSPI Timing Requirements – SDR Mode
        22. 7.10.5.22 OLDI
          1. 7.10.5.22.1 OLDI Switching Characteristics
        23. 7.10.5.23 PCIE
        24. 7.10.5.24 Timers
          1. 7.10.5.24.1 Timing Requirements for Timers
          2. 7.10.5.24.2 Switching Characteristics for Timers
        25. 7.10.5.25 UART
          1. 7.10.5.25.1 Timing Requirements for UART
          2. 7.10.5.25.2 UART Switching Characteristics
        26. 7.10.5.26 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
      4. 8.2.4 DSP C66x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 GPU
      2. 8.3.2 D5520MP2
      3. 8.3.3 VXE384MP2
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
        3. 8.4.2.3
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Peripherals
        1. 8.4.4.1  ADC
        2. 8.4.4.2  ATL
        3. 8.4.4.3  CSI
          1. 8.4.4.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.4.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 8.4.4.4  CPSW2G
        5. 8.4.4.5  CPSW9G
        6. 8.4.4.6  DCC
        7. 8.4.4.7  DDRSS
        8. 8.4.4.8  DSS
          1. 8.4.4.8.1 DSI
          2. 8.4.4.8.2 eDP
        9. 8.4.4.9  VPFE
        10. 8.4.4.10 eCAP
        11. 8.4.4.11 EPWM
        12. 8.4.4.12 ELM
        13. 8.4.4.13 ESM
        14. 8.4.4.14 eQEP
        15. 8.4.4.15 GPIO
        16. 8.4.4.16 GPMC
        17. 8.4.4.17 Hyperbus
        18. 8.4.4.18 I2C
        19. 8.4.4.19 I3C
        20. 8.4.4.20 MCAN
        21. 8.4.4.21 MCASP
        22. 8.4.4.22 MCRC Controller
        23. 8.4.4.23 MCSPI
        24. 8.4.4.24 MMC/SD
        25. 8.4.4.25 OSPI
        26. 8.4.4.26 PCIE
        27. 8.4.4.27 SerDes
        28. 8.4.4.28 WWDT
        29. 8.4.4.29 Timers
        30. 8.4.4.30 UART
        31. 8.4.4.31 USB
        32. 8.4.4.32 UFS
  9. Applications and Implementation
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for AM752x/DRA829/TDA4VM Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 SERDES REFCLK Design Guidelines
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 External Capacitors
      8. 9.3.8 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ALF|827
サーマルパッド・メカニカル・データ
発注情報

Device Comparison

Table 5-1 shows the features of the SoC, highlighting the differences.

Table 5-1 Device Comparison
FEATURES(4) REFERENCE NAME DRA829JM DRA829VM
Features
PROCESSORS AND ACCELERATORS
Speed Grades T T
Arm Cortex-A72 Microprocessor Subsystem Arm A72 Dual Core Dual Core
Arm Cortex-R5F Arm R5F Hexa Core Hexa Core
Lockstep Optional(3) Optional(3)
Device Management Security Controller DMSC Yes Yes
Security Accelerators SA Yes Yes
C7x Floating Point, Vector DSP C7x DSP Yes No
Deep Learning Accelerator MMA Yes No
Two C66x Floating Point DSP C66x DSP Dual Core No
Graphics Accelerator 3D GPU PowerVR Rogue 8XE GE8430 GPU Yes No
Depth and Motion Processing Accelerators DMPAC No No
Vision Processing Accelerators VPAC No No
Video Encoder / Decoder VENC/ VDEC Yes No
MCU Island with Lockstep Arm Cortex-R5Fs Safety Yes Yes
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM 512KB SRAM 512KB SRAM
On-Chip Shared Memory (RAM) in MCU Domain MCU_MSRAM 1MB SRAM 1MB SRAM
Multicore Shared Memory Controller MSMC 2MB (On-Chip SRAM with ECC) 2MB (On-Chip SRAM with ECC)
LPDDR4 DDR Subsystem DDRSS Up to 8GB (32-bit data) with inline ECC Up to 8GB (32-bit data) with inline ECC
SECDED 7-Bit 7-Bit
General-Purpose Memory Controller GPMC Up to 1GB with ECC Up to 1GB with ECC
PERIPHERALS
Display Subsystem DSS Yes Yes
Modular Controller Area Network Interface with Full CAN-FD Support MCAN 16 16
General-Purpose I/O GPIO Up to 226 Up to 226
Inter-Integrated Circuit Interface I2C 10 10
Improved Inter-Integrated Circuit Interface I3C 3 3
Analog-to-Digital Converter ADC 2 2
Capture Subsystem with Camera Serial Interface (CSI2) CSI2.0 4L RX 2 2
CSI2.0 4L TX 1 1
Multichannel Serial Peripheral Interface MCSPI 11 11
Multichannel Audio Serial Port MCASP0 16 Serializers 16 Serializers
MCASP1 12 Serializers 12 Serializers
MCASP2 6 Serializers 6 Serializers
MCASP3 4 Serializers 4 Serializers
MCASP4 4 Serializers 4 Serializers
MCASP5 4 Serializers 4 Serializers
MCASP6 4 Serializers 4 Serializers
MCASP7 4 Serializers 4 Serializers
MCASP8 4 Serializers 4 Serializers
MCASP9 4 Serializers 4 Serializers
MCASP10 8 Serializers 8 Serializers
MCASP11 8 Serializers 8 Serializers
MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC (8-bits) eMMC (8-bits)
MMCSD1 SD/SDIO (4-bits) SD/SDIO (4-bits)
MMCSD2 SD/SDIO (4-bits) SD/SDIO (4-bits)
Universal Flash Storage UFS 2L Yes (2 Lanes) Yes (2 Lanes)
Flash Subsystem (FSS) OSPI0 8-bits(2) 8-bits(2)
OSPI1(5) 4-bits 4-bits
HyperBus Yes(2) Yes(2)
4x PCI Express Port with Integrated PHY PCIE0 Up to Two Lanes(1) Up to Two Lanes(1)
PCIE1 Up to Two Lanes(1) Up to Two Lanes(1)
PCIE2 Up to Two Lanes(1) Up to Two Lanes(1)
PCIE3 Up to Two Lanes(1) Up to Two Lanes(1)
2x Programmable Real-Time Unit Subsystem and TSN Communication Subsystem (Ethernet Subsystem) PRU_ICSSG0 No No
PRU_ICSSG1 No No
Gigabit Ethernet Interface CPSW2G RMII or RGMII RMII or RGMII
CPSW9G 8 × RMII, 8 × RGMII, 8 × SGMII(1) 8 × RMII, 8 × RGMII, 8 × SGMII(1)
General-Purpose Timers TIMER 30 30
Enhanced High Resolution Pulse-Width Modulator Module eHRPWM 6 6
Enhanced Capture Module eCAP 3 3
Enhanced Quadrature Encoder Pulse Module eQEP 3 3
Universal Asynchronous Receiver and Transmitter UART 12 12
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY USB0 Yes(1) Yes(1)
USB1 Yes(1) Yes(1)
DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes.
Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.
Device supports features to aid in functional safety system designs such as lockstep Arm R5F if the part number is designated as R5F Lockstep capable (see Table 10-1, Nomenclature Description).
XJ721EGALF is the base part number for the superset device. Software should constrain the features used to match the intended production device.
OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.