製品の詳細

Arm CPU 1 Arm9 Arm MHz (Max.) 300 Co-processor(s) C674x DSP CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating High Temp Operating temperature range (C) -55 to 175
Arm CPU 1 Arm9 Arm MHz (Max.) 300 Co-processor(s) C674x DSP CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating High Temp Operating temperature range (C) -55 to 175
HLQFP (PTP) 176 576 mm² 24 x 24
  • Highlights
    • Dual Core SoC300-MHz ARM926EJ-S RISC MPU300-MHz C674x™ VLIW DSP
    • TMS320C674x Fixed/Floating-Point VLIW DSP Core
    • Enhanced Direct-Memory-Access Controller 3 (EDMA3)
    • 128K-Byte RAM Shared Memory
    • Two External Memory Interfaces
    • Two External Memory Interfaces Modules
    • LCD Controller
    • Two Serial Peripheral Interfaces (SPI)
    • Multimedia Card (MMC)/Secure Digital (SD)
    • Two Master/Slave Inter-Integrated Circuit
    • One Host-Port Interface (HPI)
    • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
  • Applications
    • Industrial Diagnostics
    • Test and measurement
    • Military Sonar/Radar
    • Medical measurement
    • Professional Audio
    • Down Hole Industry
  • Software Support
    • TI DSP/BIOS
    • Chip Support Library and DSP Library
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM Jazelle Technology
    • EmbeddedICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648/2736 C674x MIPS/MFLOPS
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two Level Cache Memory Architecture
    • 32K-Byte L1P Program RAM/Cache
    • 32K-Byte L1D Data RAM/Cache
    • 256K-Byte L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
    • 1024KB L2 ROM
  • Enhanced Direct-Memory-Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x™ Fixed/Floating-Point VLIW DSP Core
    • Load-Store Architecture With Non-Aligned Support
    • 64 General-Purpose Registers (32 Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and
        DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions
        Every 2 Clocks
      • Supports up to Two Floating Point (SP or DP) Approximate Reciprocal
        or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP × SP > SP Per Clock
        • 2 SP × SP > DP Every Two Clocks
        • 2 SP × DP > DP Every Three Clocks
        • 2 DP × DP > DP Every Four Clocks
        • Fixed Point Multiply Supports Two 32 × 32-Bit Multiplies,
          Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies
          per Clock Cycle, and Complex Multiples
      • Instruction Packing Reduces Code Size
      • All Instructions Conditional
      • Hardware Support for Modulo Loop Operation
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
    • 128K-Byte RAM Shared Memory
    • 3.3V LVCMOS IOs (except for USB interfaces)
    • Two External Memory Interfaces:
      • EMIFA
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
        • 16-Bit SDRAM With 128MB Address Space
      • EMIFB
        • 32-Bit or 16-Bit SDRAM With 256MB Address Space
    • Three Configurable 16550 type UART Modules:
      • UART0 With Modem Control Signals
      • Autoflow control signals (CTS, RTS) on UART0 only
      • 16-byte FIFO
      • 16x or 13x Oversampling Option
    • LCD Controller
    • Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
    • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
    • Two Master/Slave Inter-Integrated Circuit (I2CBus™)
    • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
    • Programmable Real-Time Unit Subsystem (PRUSS)
      • Two Independent Programmable Realtime Unit (PRU) Cores
        • 32-Bit Load/Store RISC architecture
        • 4K Byte instruction RAM per core
        • 512 Bytes data RAM per core
        • PRU Subsystem (PRUSS) can be disabled via software to save power
      • Standard Power Management Mechanism
        • Clock Gating
        • Entire Subsystem Under a Single PSC Clock Gating Domain
        • Dedicated Interrupt Controller
        • Dedicated Switched Central Resource
      • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
      • USB 2.0 OTG Port With Integrated PHY (USB0):
        • USB 2.0 High-/Full-Speed Client
        • USB 2.0 High-/Full-/Low-Speed Host
        • End Point 0 (Control)
        • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
      • Three Multichannel Audio Serial Ports:
        • Six Clock Zones and 28 Serial Data Pins
        • Supports TDM, I2S, and Similar Formats
        • DIT-Capable (McASP2)
        • FIFO buffers for Transmit and Receive
      • 10/100 Mb/s Ethernet MAC (EMAC):
        • IEEE 802.3 Compliant (3.3-V I/O Only)
        • RMII Media Independent Interface
        • Management Data I/O (MDIO) Module
      • Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
      • Crystal oscillators not validated beyond 125°C. Recommend use of external oscillator.
      • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
      • One 64-Bit General-Purpose Timer/Watchdog Timer (Configurable as Two 32-bit
        General-Purpose Timers)
      • Three Enhanced Pulse Width Modulators (eHRPWM):
        • Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
        • 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
        • Dead-Band Generation
        • PWM Chopping by High-Frequency Carrier
        • Trip Zone Input
      • Three 32-Bit Enhanced Capture Modules (eCAP):
        • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs
        • Single Shot Capture of up to Four Event Time-Stamps
      • Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)
      • 176-pin PowerPADTM Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
      • High Temperature (175°C) Application
      • Texas Instruments High Temperature Products Use Highly Optimized Silicon Solutions with
        Design and Process Enhancements to Maximize Performance over Extended Temperatures.
        All Devices are Characterized and Qualified for 1000 Hours Continuous Operating Life
        at Maximum Rated Temperature
      • Community Resources
        • TI E2E Community
        • TI Embedded Processors Wiki

  • Highlights
    • Dual Core SoC300-MHz ARM926EJ-S RISC MPU300-MHz C674x™ VLIW DSP
    • TMS320C674x Fixed/Floating-Point VLIW DSP Core
    • Enhanced Direct-Memory-Access Controller 3 (EDMA3)
    • 128K-Byte RAM Shared Memory
    • Two External Memory Interfaces
    • Two External Memory Interfaces Modules
    • LCD Controller
    • Two Serial Peripheral Interfaces (SPI)
    • Multimedia Card (MMC)/Secure Digital (SD)
    • Two Master/Slave Inter-Integrated Circuit
    • One Host-Port Interface (HPI)
    • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
  • Applications
    • Industrial Diagnostics
    • Test and measurement
    • Military Sonar/Radar
    • Medical measurement
    • Professional Audio
    • Down Hole Industry
  • Software Support
    • TI DSP/BIOS
    • Chip Support Library and DSP Library
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM Jazelle Technology
    • EmbeddedICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648/2736 C674x MIPS/MFLOPS
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two Level Cache Memory Architecture
    • 32K-Byte L1P Program RAM/Cache
    • 32K-Byte L1D Data RAM/Cache
    • 256K-Byte L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
    • 1024KB L2 ROM
  • Enhanced Direct-Memory-Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x™ Fixed/Floating-Point VLIW DSP Core
    • Load-Store Architecture With Non-Aligned Support
    • 64 General-Purpose Registers (32 Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and
        DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions
        Every 2 Clocks
      • Supports up to Two Floating Point (SP or DP) Approximate Reciprocal
        or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP × SP > SP Per Clock
        • 2 SP × SP > DP Every Two Clocks
        • 2 SP × DP > DP Every Three Clocks
        • 2 DP × DP > DP Every Four Clocks
        • Fixed Point Multiply Supports Two 32 × 32-Bit Multiplies,
          Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies
          per Clock Cycle, and Complex Multiples
      • Instruction Packing Reduces Code Size
      • All Instructions Conditional
      • Hardware Support for Modulo Loop Operation
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
    • 128K-Byte RAM Shared Memory
    • 3.3V LVCMOS IOs (except for USB interfaces)
    • Two External Memory Interfaces:
      • EMIFA
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
        • 16-Bit SDRAM With 128MB Address Space
      • EMIFB
        • 32-Bit or 16-Bit SDRAM With 256MB Address Space
    • Three Configurable 16550 type UART Modules:
      • UART0 With Modem Control Signals
      • Autoflow control signals (CTS, RTS) on UART0 only
      • 16-byte FIFO
      • 16x or 13x Oversampling Option
    • LCD Controller
    • Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
    • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
    • Two Master/Slave Inter-Integrated Circuit (I2CBus™)
    • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
    • Programmable Real-Time Unit Subsystem (PRUSS)
      • Two Independent Programmable Realtime Unit (PRU) Cores
        • 32-Bit Load/Store RISC architecture
        • 4K Byte instruction RAM per core
        • 512 Bytes data RAM per core
        • PRU Subsystem (PRUSS) can be disabled via software to save power
      • Standard Power Management Mechanism
        • Clock Gating
        • Entire Subsystem Under a Single PSC Clock Gating Domain
        • Dedicated Interrupt Controller
        • Dedicated Switched Central Resource
      • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
      • USB 2.0 OTG Port With Integrated PHY (USB0):
        • USB 2.0 High-/Full-Speed Client
        • USB 2.0 High-/Full-/Low-Speed Host
        • End Point 0 (Control)
        • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
      • Three Multichannel Audio Serial Ports:
        • Six Clock Zones and 28 Serial Data Pins
        • Supports TDM, I2S, and Similar Formats
        • DIT-Capable (McASP2)
        • FIFO buffers for Transmit and Receive
      • 10/100 Mb/s Ethernet MAC (EMAC):
        • IEEE 802.3 Compliant (3.3-V I/O Only)
        • RMII Media Independent Interface
        • Management Data I/O (MDIO) Module
      • Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
      • Crystal oscillators not validated beyond 125°C. Recommend use of external oscillator.
      • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
      • One 64-Bit General-Purpose Timer/Watchdog Timer (Configurable as Two 32-bit
        General-Purpose Timers)
      • Three Enhanced Pulse Width Modulators (eHRPWM):
        • Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
        • 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
        • Dead-Band Generation
        • PWM Chopping by High-Frequency Carrier
        • Trip Zone Input
      • Three 32-Bit Enhanced Capture Modules (eCAP):
        • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs
        • Single Shot Capture of up to Four Event Time-Stamps
      • Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)
      • 176-pin PowerPADTM Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
      • High Temperature (175°C) Application
      • Texas Instruments High Temperature Products Use Highly Optimized Silicon Solutions with
        Design and Process Enhancements to Maximize Performance over Extended Temperatures.
        All Devices are Characterized and Qualified for 1000 Hours Continuous Operating Life
        at Maximum Rated Temperature
      • Community Resources
        • TI E2E Community
        • TI Embedded Processors Wiki

The OMAPL137 is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAPL137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAPL137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16Kbyte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The OMAPL137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) bus interfaces; 3 multichannel audio serial ports (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The OMAPL137 is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAPL137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAPL137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16Kbyte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The OMAPL137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) bus interfaces; 3 multichannel audio serial ports (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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技術資料

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11 資料すべて表示
種類 タイトル 英語版のダウンロード 日付
* データシート Low-Power Applications Processor データシート (Rev. B) 2013年 2月 8日
* エラッタ OMAP-L137 C6000 DSP+ARM Processor Errata (Silicon Revs 3.0, 2.1, 2.0, 1.1 & 1.0) (Rev. I) 2014年 6月 17日
* 放射線と信頼性レポート OMAPL137PTPH Reliability Report (Rev. A) 2012年 8月 17日
技術記事 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技術記事 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
アプリケーション・ノート Processor SDK RTOS Audio Benchmark Starterkit 2017年 4月 12日
ユーザー・ガイド OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) 2016年 9月 21日
技術記事 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
技術記事 TI's new DSP Benchmark Site 2016年 2月 8日
アプリケーション・ノート Power Consumption Guide for the C66x 2011年 10月 6日
ホワイト・ペーパー Middleware/Firmware design challenges due to dynamic raw NAND market 2011年 5月 19日

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デバッグ・プローブ

TMDSEMU200-U — Spectrum Digital XDS200 USB エミュレータ

Spectrum Digital XDS200 は、TI のプロセッサを対象とする最新の XDS200 デバッグ・プローブ(エミュレータ)ファミリの最初のモデルです。XDS200 ファミリは、超低コストの XDS100 と高性能の XDS560v2 の間で、低コストと高性能の最適バランスを実現します。また、すべての XDS デバッグ・プローブは、ETB(Embedded Trace Buffer、組込みトレース・バッファ)を搭載したすべての ARM と DSP プロセッサに対し、コア・トレースとシステム・トレースをサポートしています。

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The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

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TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

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MATHLIB — DSP 演算ライブラリ、浮動小数点デバイス用

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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SPRC265 — C64x+DSPLIB

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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C66XCODECS — コーデック - ビデオ、スピーチ - C66x ベース・デバイス用

TI のコーデックは無償であり、量産ライセンスが付属しているほか、今すぐダウンロードできます。いずれも量産テスト済みで、ビデオや音声の各アプリケーションに簡単に統合可能です。多くの場合、C66x プラットフォーム向けの C64x+ コーデックが提供済みであり、検証済みです。各インストーラやダウンロード・ページから、データシートとリリース・ノートが利用可能です。

下記の 「Download options」 (オプションのダウンロード) ボタンを使用して入手できるコーデックは、TI が現時点で提供している、最新のテスト済みバージョンです。さらに、一部のアプリケーション・デモで、TI (...)

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PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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