The SN74LVC1G38 device is designed for 1.65-V to 5.5-V VCC operation.
This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A × B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
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|Part number||オーダー・オプション||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Inputs per channel||IOL (Max) (mA)||IOH (Max) (mA)||Input type||Output type||Features||Rating||Data rate (Max) (Mbps)||Operating temperature range (C)||Package size: mm2:W x L (PKG)||Package Group|
Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)
-40 to 125
-40 to 85
5DSBGA: 2 mm2: 1.25 x 1.75 (DSBGA | 5)
5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)
6SON: 1 mm2: 1 x 1 (SON | 6)
6SON: 1 mm2: 1 x 1.45 (SON | 6)
5SOT-23: 5 mm2: 1.6 x 2.9 (SOT-23 | 5)
5X2SON: 1 mm2: .8 x .8 (X2SON | 5)
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
X2SON | 5