Low power C55x fixed point DSP- up to 150MHz, USB, LCD interface, FFT HWA, SAR ADC
製品の詳細
パラメータ
パッケージ|ピン|サイズ
特長
- High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
- 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
- 60-, 75-, 100-, 120-, 150-MHz Clock Rate
- One/Two Instructions Executed per Cycle
- Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
- Two Arithmetic/Logic Units (ALUs)
- Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
- Software-Compatible With C55x Devices
- Industrial Temperature Devices Available
- 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
- 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
- 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
- 128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit) - 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
- 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
- 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
- 8-/16-Bit NOR Flash
- Asynchronous Static RAM (SRAM)
- 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
- Direct Memory Access (DMA) Controller
- Four DMA With 4 Channels Each (16-Channels Total)
- Three 32-Bit General-Purpose Timers
- One Selectable as a Watchdog and/or GP
- Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
- Universal Asynchronous Receiver/Transmitter (UART)
- Serial-Port Interface (SPI) With Four Chip-Selects
- Master/Slave Inter-Integrated Circuit (I2C Bus™)
- Four Inter-IC Sound (I2S Bus™) for Data Transport
- Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
- USB 2.0 Full- and High-Speed Device
- LCD Bridge With Asynchronous Interface
- Tightly-Coupled FFT Hardware Accelerator
- 10-Bit 4-Input Successive Approximation (SAR) ADC
- Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
- Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
- Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
- One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA)
- Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
- On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
- IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible - Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions) - 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
- 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
- 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
- 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os
All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.
概要
The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.
The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.
The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.
The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL) and 10-bit SAR ADC(VDDA_ANA). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL).
The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
Limited design support from TI available
This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.
技術資料
設計と開発
追加の事項や他のリソースを参照するには、以下のタイトルをクリックすると、詳細ページを表示できます。ハードウェア開発
概要
The TMDX5505eZDSP is a small form factor, very low cost USB-powered DSP development tool which includes all the hardware and software needed to evaluate the industry's lowest power 16-bit DSP: TMS320C5504 and TMS320C5505. The USB port provides enough power to operate the ultra-low-power C5505 so no (...)
特長
The TMS320C5504 and TMS320C5505 are industry's lowest power 16-bit processors helping conserve energy at exceptional levels and enabling longer battery life. With 200 MIPS performance, upto 320KB on-chip memory, higher integration (including a hardware accelerator for FFT computation) than (...)
概要
The TMDX5515eZDSP is a small form factor, very low cost USB-powered DSP development tool which includes all the hardware and software needed to evaluate the industry’s lowest power 16-bit DSP : TMS320C5515. This tool is similar to TMDX5505eZdsp in the form factor but provides more evaluation (...)
特長
The TMS320C5514 and TMS320C5515 are industry’s lowest power 16-bit processors helping conserve energy at exceptional levels and enabling longer battery life. With 240 MIPS performance, upto 320KB on-chip memory, higher integration (including a hardware accelerator for FFT computation) than (...)
概要
Spectrum Digital XDS200 は、TI のプロセッサを対象とする最新の XDS200 デバッグ・プローブ(エミュレータ)ファミリの最初のモデルです。XDS200 ファミリは、超低コストの XDS100 と高性能の XDS560v2 の間で、低コストと高性能の最適バランスを実現します。また、すべての XDS デバッグ・プローブは、ETB(Embedded Trace Buffer、組込みトレース・バッファ)を搭載したすべての ARM と DSP プロセッサに対し、コア・トレースとシステム・トレースをサポートしています。
Spectrum Digital XDS200 は、TI 20 ピン・コネクタ(TI 14 ピン、ARM 10 ピン、ARM 20 ピンを接続するための複数のアダプタ付属)とホスト側の USB 2.0 (...)
特長
XDS200 は、TI のプロセッサを対象とする最新の JTAG デバッグ・プローブ(エミュレータ)ファミリです。高い性能と一般的な機能を搭載した低コスト XDS100 と高性能 XDS560v2 の中間に位置する XDS200 は、TI のマイコン、プロセッサ、ワイヤレス・デバイスのデバッグのためのバランス重視のソリューションを提供します。
XDS200 は、販売開始から長い年月が経過している「XDS510」JTAG デバッガ・ファミリに比べ、データ・スループットが高いほか、ARM シリアル・ワイヤ・デバッグ・モードのサポート機能も追加しており、コスト低減を可能にします。
TI では開発ボードのスペース低減を推進しており、すべての XDS200 派生製品は、ターゲット接続用のプライマリ JTAG コネクティビティとして標準的な TI 20 ピン・コネクタを実装しています。この製品に加えて、すべての派生製品は、TI と ARM の標準的な JTAG ヘッダーに接続するためにモジュラー形式のターゲット構成アダプタも採用しています(付属するアダプタは、モデルによって異なります)。
XDS200 は、従来型の IEEE1149.1(JTAG)、IEEE1149.7(cJTAG)、ARM のシリアル・ワイヤ・デバッグ(SWD)とシリアル・ワイヤ出力(SWO)をサポートしており、+1.5V ~ 4.1V のインターフェイス・レベルで動作します。
IEEE1149.7 つまり Compact JTAG(cJTAG)は、従来型の JTAG を大幅に改良しており、2 本のピンだけで従来型のすべての機能をサポートします。また、TI のワイヤレス・コネクティビティ・マイコンでの利用も可能です。
シリアル・ワイヤ・デバッグ(SWD)とは、同じく 2 本のピンを使用して、JTAG より高速なクロック・レートでデータを転送するデバッグ・モードです。シリアル・ワイヤ出力(SWO)を使用する場合は、もう 1 本のピンを追加して、Cortex M4 マイコンで簡潔なトレース動作を実行することができます。
すべての XDS200 モデルは、ホストへの接続のために、USB2.0 ハイスピード(480Mbps)をサポートしており、一部のモデルではイーサネット 10/100Mbps もサポートしています。また、一部のモデルではターゲット・ボードでの消費電力監視をサポートしています。
XDS200 ファミリには、TI の (...)
概要
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
特長
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
概要
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
特長
-
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
ソフトウェア開発
特長
- C55x CSL(SPRC133): この機能セクションに掲載されている機能は、C5501、C5502、C5509、C5509A、C5510、C5510A を含む TMS320C55x DSP 向けに設計されたものです。
- C55x CSL - Low Power (低消費電力): features (特長) セクションに掲載されている機能は、C5504 / 05、C5514 / 15 / 17、C5535 / 45 の各デバイスを含む TMS320C55x 低消費電力 DSP 向けの特化型設計を採用しています。
特長
モジュール 名前 | C55x CSL - SPRC133 ペリフェラルの概要 | モジュール 名前 | C55x CSL - Low Power CSL (低消費電力 CSL) ペリフェラルの概要 |
ADC | A/D コンバータ | 逐次比較型 | 10 ビット SAR ADC |
ICACHE | 命令キャッシュ | ||
DAT | デバイスに依存しない データのコピー / 大量生成 | DAT | データのコピー / 大量生成モジュール DMA C5505 がベース |
DMA | ダイレクト・メモリ・アクセス | DMA | ダイレクト・メモリ・アクセス |
IRQ | 割り込みコントローラ | INTC | 割り込みコントローラ |
EMIF | 外部メモリ・インターフェイス | NAND | NAND (...) |
特長
Image Analysis
- Image boundry and perimeter
- Morphological operation
- Edge detection
- Image Histogram
- Image thresholding
Image filtering and format conversion
- Color space conversion
- Image convolution
- Image correlation
- Error diffusion
- Median filtering
- Pixel expansion
Image compression and decompression
- Forward and (...)
特長
C55x Codecs are optimized for use on any TM320C55x™ devices. C55x Codecs offer:
- Free, object code with production licensing
- WINDOWS installers
- C55x Audio Codecs were tested on C5505 and C5510 devices
- C55x Speech Codecs were tested on C5510 device
- All codecs are eXpressDSP™ compliant
- Performance data are (...)
Vocal Technologies の詳細については https://www.vocal.com をご覧ください。
設計ツールとシミュレーション
特長
- Supports many TI processors including Sitara and Jacinto Processors and DSPs
- Search by type of product, TI devices supported, or country
- Links and contacts for quick engagement
- Third-party companies located around the world
CAD/CAE シンボル
パッケージ | ピン数 | ダウンロード |
---|---|---|
NFBGA (ZCH) | 196 | オプションの表示 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL rating/ リフローピーク温度
- MTBF/FIT の推定値
- 原材料組成
- 認定試験結果
- 継続的な信頼性モニタ試験結果