TPS7H3x01 シンク/ソース DDR 終端レギュレータ - TPS7H3301-SP

TPS7H3301-SP (供給中)

TPS7H3x01 シンク/ソース DDR 終端レギュレータ

 

概要

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically design to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports and is compliant to DDR, DDR2, DDR3, DDR4, and associated low-power JEDEC specifications. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT during suspend to RAM (S3) power down mode.

特長

  • 5962R14288(1):
    • Radiation Hardness Assurance (RHA) Qualified to Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-Up (SEL), Single Event Gate Rupture (SEGR), Single Event Burnout (SEB) Immune to LET = 65 MeV-cm2/mg
    • SET, SEFI, SEU Immune to 65 MeV-cm2/mg
  • Supports DDR, DDR2, DDR3, DDR3LP, and DDR4 Termination Applications and is Compliant to JEDEC Standards
  • Input Voltage: Supports a 2.5-V and 3.3-V Rail(2)
  • Separate Low-Voltage Input (VLDOIN) Down to .9 V for Improved Power Efficiency(2)
  • 3-A Sink and Source Termination Regulator Includes Droop Compensation
  • Enable Input and Power-Good Output for Power Supply Sequencing
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 to 1.75 V
    • 3-A Sink and Source Current
    • ±20-mV Accuracy
  • Integrated Precision Voltage Divider Network With Sense Input
  • Remote Sensing (VOSNS)
  • VTTREF Buffered Reference
    • VDDQ/2 ±1% Accuracy
    • ±10-mA Sink and Source Current
  • Undervoltage Lockout (UVLO), and Overcurrent Limit (OCL) Functionality Integrated

All trademarks are the property of their respective owners.
(1)For all available packages, see the orderable addendum at the end of the data sheet.
(2) Applicable to DDR2, DDR3, DDR3L and DDR4. For DDR, input voltage = 3.3-V nominal. VIN is 2.95 to 3.5 V for DDR1 and VLDOIN > VTT for all DDRs. For DDR2 3-A load condition, VIN is 2.45 to 3.5 V. VIN headroom: VIN_MIN ≥ VTT + 1.5 V.
(3) These units are intended for engineering evaluation only. They are processed to a noncompliant flow (that is, no burn-in, and so forth) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.

詳細を表示

機能一覧 他の製品と比較 DDR メモリ電源製品

 
DDR Memory Type
Iout VTT (Max) (A)
Iq (Typ) (mA)
Output
Vin (Min) (V)
Vin (Max) (V)
Special Features
Rating
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
Regulator Type
Vout VTT (Min) (V)
TPS7H3301-SP
DDR
DDR2
DDR3
DDR3L
DDR4
LPDDR2
LPDDR3   
3   
18   
VREF
VTT   
0.9   
3.5   
Complete Solution
PGOOD
Shutdown Pin for S3   
Space   
-55 to 125
25 only   
CFP   
See datasheet (CFP)   
Linear Regulator   
0.6   

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