CDCDB400
- 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
- 4 hardware output enable (OE#) controls
- Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
- Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
- Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
- Supports Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Output-to-output skew: < 50 ps
- Input-to-output delay: < 3 ns
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Fail-safe input
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Programmable output slew rate control
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3 selectable SMBus addresses
- 3.3-V core and IO supply voltages
- Hardware-controlled low power mode (PD#)
- Current consumption: 46 mA maximum
- 5-mm × 5-mm, 32-pin VQFN package
The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | CDCDB400 DB800ZL-Compliant 4-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A) | PDF | HTML | 23 May 2022 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
CDCDB800EVM — CDCDB800 evaluation module is an 8-output LP-HCSL clock buffer for PCIe® Gen 1 to Gen 5 application
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
VQFN (RHB) | 32 | View options |
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