LMK00334-Q1
Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator
LMK00334-Q1
- AEC-Q100 Qualified for Automotive Applications:
- Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C5
- Device MM ESD Classification Level M2
- 3:1 Input multiplexer
- Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
- One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
- Two banks with two differential outputs each
- HCSL, or Hi-Z (selectable)
- Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:
- 30 fs RMS (typical)
- High PSRR: –72 dBc at 156.25 MHz
- LVCMOS output with synchronous enable input
- Pin-controlled configuration
- VCC core supply: 3.3 V ± 5%
- Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
- Industrial temperature range: –40°C to +105°C
- 32-pin WQFN (5 mm × 5 mm)
The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.
The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.
The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | LMK00334-Q1 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5 datasheet (Rev. A) | PDF | HTML | 19 Jan 2022 |
Application note | Clocking for PCIe Applications | PDF | HTML | 28 Nov 2023 | |
EVM User's guide | LMK00338EVM User's Guide | 13 Dec 2013 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
LMK00338EVM — LMK00338 PCIe Gen1/2/3 Clock Buffer Evaluation Module
The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
WQFN (RTV) | 32 | View options |
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