LMK1C1102
- High-performance 1:2, 1:3 or 1:4 LVCMOS clock buffer
- Very low output skew < 50 ps
- Extremely low additive jitter < 50 fs maximum
- 7.5 fs typical at VDD = 3.3 V
- 10 fs typical at VDD = 2.5 V
- 19.2 fs typical at VDD = 1.8 V
- Very low propagation delay < 3 ns
- Synchronous output enable
- Supply voltage: 3.3 V, 2.5 V, or 1.8 V
- 3.3-V tolerant input at all supply voltages
- Fail-safe inputs
- fmax = 250 MHz for 3.3 V fmax = 200 MHz for 2.5 V and 1.8 V
- Operating temperature range: –40°C to 125°C
- Available in 8-pin TSSOP package
- Available in 8-pin WSON package
The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Three different fan-out variations, 1:2, 1:3, 1:4, are available.
All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.
All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.
The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.
The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family datasheet (Rev. D) | PDF | HTML | 18 Feb 2022 |
Application note | LMK1C110x Key Performance in System Level (Rev. A) | 10 Mar 2020 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
LMK1C1104EVM — LMK1C1104 low jitter 1:4 LVCMOS fan-out buffer evaluation module
LMK1C1108EVM — LMK1C1108 low jitter 1:8 LVCMOS fan-out buffer evaluation module
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
TSSOP (PW) | 8 | View options |
WSON (DQF) | 8 | View options |
Ordering & quality
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- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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