CDCLVP2102
- Dual 1:2 Differential Buffer
- Two Clock Inputs
- Universal Inputs Can Accept LVPECL,
LVDS, LVCMOS/LVTTL - Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption:
48 mA - Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range - 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Within Bank Output Skew: 10 ps
- LVPECL Reference Voltage, VAC_REF,
Available for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C
to +85°C - Supports 105°C PCB Temperature
(Measured with a Thermal Pad) - Available in 3-mm × 3-mm, 16-Pin
VQFN (RGT) Package - ESD Protection Exceeds 2000 V (HBM)
The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2102 is characterized for operation from 40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. C) | PDF | HTML | 25 Oct 2013 |
User guide | CDCLVP2102 User's Guide | 09 Jul 2009 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
CDCLVP2102EVM — CDCLVP2102 Evaluation Module
The CDCLVP2102 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, and each input feeds a bank of two LVPECL outputs. The device also features on-chip bias generators that can provide the (...)
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
VQFN (RGT) | 16 | View options |
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