LMK1D1212
- High-performance LVDS clock buffer family: up to 2 GHz
- 2:12 differential buffer (LMK1D1212)
- 2:16 differential buffer (LMK1D1216)
- Supply voltage: 1.71 V to 3.465 V
- Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
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Very low phase noise floor: -164 dBc/Hz (typical)
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Very low propagation delay: < 575 ps maximum
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Output skew: 20 ps maximum
- High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
- Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
- LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
- Industrial temperature range: –40°C to 105°C
- Packaged in
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LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)
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LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)
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The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.
The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
Technical documentation
Type | Title | Date | ||
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* | Data sheet | LMK1D121x Low Additive Jitter LVDS Buffer datasheet (Rev. A) | PDF | HTML | 12 Apr 2023 |
User guide | LMK1D1212EVM User's Guide | PDF | HTML | 26 Oct 2021 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
LMK1D1212EVM — LMK1D1212 low jitter 2:12 LVDS fan-out buffer evaluation module
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
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VQFN (RHA) | 40 | View options |
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