製品の詳細

DSP 1 C67x DSP MHz (Max) 167, 200, 250 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
DSP 1 C67x DSP MHz (Max) 167, 200, 250 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
BGA (GDP) 272 729 mm² 27 x 27 BGA (ZDP) 272 729 mm² 27 x 27
  • Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6711D
    • Eight 32-Bit Instructions/Cycle
    • 167-, 200-, 250-MHz Clock Rates
    • 6-, 5-, 4-ns Instruction Cycle Time
    • 1000, 1200, 1500 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/O, 1.4-V Internal (-250)
  • 3.3-V I/O, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D.

  • Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6711D
    • Eight 32-Bit Instructions/Cycle
    • 167-, 200-, 250-MHz Clock Rates
    • 6-, 5-, 4-ns Instruction Cycle Time
    • 1000, 1200, 1500 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/O, 1.4-V Internal (-250)
  • 3.3-V I/O, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D.

The TMS320C67x™ DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices) compose the floating-point DSP family in the TMS320C6000™ DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.

The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C67x™ DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices) compose the floating-point DSP family in the TMS320C6000™ DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.

The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

ダウンロード

Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

技術資料

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25 資料すべて表示
種類 タイトル 英語版のダウンロード 日付
* データシート TMS320C6711D Floating-Point Digital Signal Processor データシート (Rev. B) 2006年 6月 30日
* エラッタ TMS320C6711/C6711B/C6711C/C6711D DSPs Errata-Revs 1.0, 1.1, 1.2, 1.3, 2.0, 2.1) (Rev. P) 2005年 8月 12日
アプリケーション・ノート How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) 2021年 5月 19日
技術記事 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技術記事 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
技術記事 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
技術記事 TI's new DSP Benchmark Site 2016年 2月 8日
アプリケーション・ノート Power Consumption Guide for the C66x 2011年 10月 6日
ユーザー・ガイド TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009年 7月 2日
アプリケーション・ノート TMS320DM64xx、TMS320DM64x、および TMS320C6000 デバイスにおける熱考察 英語版をダウンロード 2008年 5月 5日
ユーザー・ガイド TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007年 4月 11日
ユーザー・ガイド TMS320C6000 DSP Multichannel Buffered Serial Port ( McBSP) Reference Guide (Rev. G) 2006年 12月 14日
ユーザー・ガイド TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006年 11月 15日
ユーザー・ガイド TMS320C6000 DSP エンハンスト・ダイレクト・メモリ・アクセス (EDMA) コントローラ (Rev. B 翻訳版) 最新の英語版をダウンロード (Rev.C) 2006年 11月 6日
ユーザー・ガイド TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006年 1月 1日
アプリケーション・ノート Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H) 2005年 11月 10日
ユーザー・ガイド TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005年 3月 1日
ユーザー・ガイド TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005年 1月 25日
ユーザー・ガイド TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG (Rev. C) 2004年 8月 2日
ユーザー・ガイド TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 2004年 6月 8日
アプリケーション・ノート TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A) 2004年 5月 31日
ユーザー・ガイド TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004年 3月 25日
アプリケーション・ノート TMS320C6000 EDMA IO Scheduling and Performance 2004年 3月 5日
アプリケーション・ノート TMS320C621x/671x EDMA Performance Data 2004年 3月 5日
アプリケーション・ノート TMS320C621x/TMS320C671x EDMA Architecture 2004年 3月 5日

設計と開発

追加の事項や他のリソースを参照するには、以下のタイトルをクリックすると、詳細ページを表示できます。

デバッグ・プローブ

TMDSEMU560V2STM-U — Blackhawk XDS560v2 システム・トレース USB エミュレータ

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

在庫あり
制限: 1
デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

在庫あり
制限: 1
ドライバまたはライブラリ

MATHLIB — DSP 演算ライブラリ、浮動小数点デバイス用

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
ドライバまたはライブラリ

SPRC265 — C64x+DSPLIB

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
ドライバまたはライブラリ

TELECOMLIB — テレコムおよびメディア向けライブラリ - FAXLIB、VoLIB および AEC/AER、TMS320C64x+ および TMS320C55x プロセッサ用

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
シミュレーション・モデル

C6711D GDP IBIS Model

SPRM145.ZIP (69 KB) - IBIS Model
シミュレーション・モデル

C6711D GDP BSDL Model

SPRM216.ZIP (6 KB) - BSDL Model
設計ツール

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
パッケージ ピン数 ダウンロード
BGA (GDP) 272 オプションの表示
BGA (ZDP) 272 オプションの表示

購入と品質

含まれる情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL rating/ リフローピーク温度
  • MTBF/FIT の推定値
  • 原材料組成
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果

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