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リニア・レギュレータと低ドロップアウト (LDO) レギュレータ

TPS70751-EP

アクティブ

エンハンスド製品、起動シーケンシング機能搭載、デュアル出力、低ドロップアウト (LDO) 電圧レギュレータ

ご注文はこちら
データシート

この製品には新バージョンがあります。

open-in-new 代替品と比較
比較対象デバイスと同等の機能で、ピン配置が異なる製品
TPS7A88-Q1 アクティブ 車載、1A、低ノイズ、高精度、デュアルチャネル、調整可能な低ドロップアウト電圧レギュレータ Lower noise in smaller 4 x 4 VQFN
比較対象デバイスと類似の機能
TPS7A87 アクティブ 500mA、低ノイズ、高 PSRR、デュアルチャネル、調整可能な超低ドロップアウト電圧レギュレータ Alternative dual LDO with ultra-low-noise performance in a 4-mm x 4-mm WQFN package.

TPS70751-EP

アクティブ
データシート ご注文はこちら

製品詳細

Output options Dual output, Fixed Output Iout (max) (A) 0.25 Vin (max) (V) 6 Vin (min) (V) 2.7 Vout (max) (V) 3.3 Vout (min) (V) 3.3 Fixed output options (V) 1.8, 3.3 Noise (µVrms) 65 Iq (typ) (mA) 0.19 Thermal resistance θJA (°C/W) 33 Rating HiRel Enhanced Product Load capacitance (min) (µF) 10 Regulated outputs (#) 2 Features Enable, Output discharge, Power good, Sequencing and monitoring Accuracy (%) 2 PSRR at 100 KHz (dB) 10 Dropout voltage (Vdo) (typ) (mV) 83 Operating temperature range (°C) -55 to 125
Output options Dual output, Fixed Output Iout (max) (A) 0.25 Vin (max) (V) 6 Vin (min) (V) 2.7 Vout (max) (V) 3.3 Vout (min) (V) 3.3 Fixed output options (V) 1.8, 3.3 Noise (µVrms) 65 Iq (typ) (mA) 0.19 Thermal resistance θJA (°C/W) 33 Rating HiRel Enhanced Product Load capacitance (min) (µF) 10 Regulated outputs (#) 2 Features Enable, Output discharge, Power good, Sequencing and monitoring Accuracy (%) 2 PSRR at 100 KHz (dB) 10 Dropout voltage (Vdo) (typ) (mV) 83 Operating temperature range (°C) -55 to 125
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power-Up Sequencing for DSP Applications (See Part Number TPS708xx for Independently Enabled Outputs)
  • Output Current Range of 250 mA on Regulator 1 and 125 mA on Regulator 2
  • Fast Transient Response
  • 3.3-V/1.8-V Fixed Voltage Outputs
  • Open-Drain Power-On Reset With 120-ms Delay
  • Open-Drain Power Good for Regulator 1
  • Ultralow 190-µA (Typ) Quiescent Current
  • 1-µA Input Current During Standby
  • Low Noise: 65 µVrms Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 20-Pin PowerPAD™ Thin Shrink Small-Outline Package (TSSOP)
  • Thermal Shutdown Protection

PowerPAD Is a trademark of Texas Instruments

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power-Up Sequencing for DSP Applications (See Part Number TPS708xx for Independently Enabled Outputs)
  • Output Current Range of 250 mA on Regulator 1 and 125 mA on Regulator 2
  • Fast Transient Response
  • 3.3-V/1.8-V Fixed Voltage Outputs
  • Open-Drain Power-On Reset With 120-ms Delay
  • Open-Drain Power Good for Regulator 1
  • Ultralow 190-µA (Typ) Quiescent Current
  • 1-µA Input Current During Standby
  • Low Noise: 65 µVrms Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 20-Pin PowerPAD™ Thin Shrink Small-Outline Package (TSSOP)
  • Thermal Shutdown Protection

PowerPAD Is a trademark of Texas Instruments

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The TPS707xx family devices are designed to provide a complete power-management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual-output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP applications with power-sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution.

The TPS707xx family of voltage regulators offer very low dropout (LDO) voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors.

The TPS70751 has a fixed voltage of 3.3 V/1.8 V. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.

The device is enabled when the enable (EN) pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.

The input signal at the sequence (SEQ) pin controls the power-up sequence of the two regulators. When the device is enabled and SEQ is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time, VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e., overload condition), VOUT1 is turned off. Pulling SEQ low reverses the power-up order and VOUT1 is turned on first. SEQ is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The power good (PG1) pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the circuitry supplied by regulator 1.

The TPS70751 features a RESET (SVS, POR, or power-on reset). The RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset (MR1 and MR2) pins. When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high-impedance state after a 120-ms delay. RESET goes to logic low state when VOUT2 regulated output voltage is pulled below 95% (i.e., overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output can be connected to MR1 or MR2.

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5 V.

The TPS707xx family devices are designed to provide a complete power-management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual-output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP applications with power-sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution.

The TPS707xx family of voltage regulators offer very low dropout (LDO) voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 10-µF low ESR capacitors.

The TPS70751 has a fixed voltage of 3.3 V/1.8 V. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.

The device is enabled when the enable (EN) pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.

The input signal at the sequence (SEQ) pin controls the power-up sequence of the two regulators. When the device is enabled and SEQ is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time, VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e., overload condition), VOUT1 is turned off. Pulling SEQ low reverses the power-up order and VOUT1 is turned on first. SEQ is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The power good (PG1) pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the circuitry supplied by regulator 1.

The TPS70751 features a RESET (SVS, POR, or power-on reset). The RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset (MR1 and MR2) pins. When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high-impedance state after a 120-ms delay. RESET goes to logic low state when VOUT2 regulated output voltage is pulled below 95% (i.e., overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output can be connected to MR1 or MR2.

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5 V.
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技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート TPS70751-EP データシート 2006年 9月 25日
* VID TPS70751-EP VID V6207610 2016年 6月 21日
アプリケーション・ノート LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
アプリケーション・ノート LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日

設計と開発

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パッケージ ピン数 ダウンロード
HTSSOP (PWP) 20 オプションの表示
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購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点

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